20P/SOIC (ROHS)

ATMEL-AT89C2051

8-bit MCU with 2K Bytes Flash

 
 
 
Features
 
 

●Compatible with MCS®-51Products
●2K Bytes of Reprogrammable Flash Memory 
– Endurance: 10,000 Write/Erase Cycles
●2.7V to 6V Operating Range
●Fully Static Operation: 0 Hz to 24 MHz
●Two-level Program Memory Lock
●128 x 8-bit Internal RAM
●15 Programmable I/O Lines
●Two 16-bit Timer/Counters
●Six Interrupt Sources
●Programmable Serial UART Channel
●Direct LED Drive Outputs
●On-chip Analog Comparator
●Low-power Idle and Power-down Modes
●Green (Pb/Halide-free) Packaging Option

 
 
 
Description
 
 

The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with 2K bytes of Flash programmable and erasable read-only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a power-ful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. 
The AT89C2051 provides the following standard features: 2K bytes of Flash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C2051 is designed with static logic for opera-tion down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

 
 
 
Pin Configuration
 
 

 
 
 
Block Diagram
 
 

 
 
 
Pin Description
 
 

 
 
 
Oscillator Characteristics
 
 

 
 
 
Special Function Registers
 
 

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in the table below. Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-mented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

 
 
 
Restrictions on Certain Instructions
 
 

 
 
 
Program Memory Lock Bits
 
 

 
 
 
Idle Mode
 
 

 In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. 
The P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if external pull-ups are used. 
It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

 
 
 
Power-down Mode
 
 

In the power-down mode the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. 
The P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if external pull-ups are used.

 
 
 
Programming The Flash
 
 

The AT89C2051 is shipped with the 2K bytes of on-chip PEROM code memory array in the erased state (i.e., contents = FFH) and ready to be programmed. The code memory array is pro-grammed one byte at a time. Once the array is programmed, to re-program any non-blank byte, the entire memory array needs to be erased electrically.
 Internal Address Counter: The AT89C2051 contains an internal PEROM address counter which is always reset to 000H on the rising edge of RST and is advanced by applying a positive going pulse to pin XTAL1. 
Programming Algorithm: To program the AT89C2051, the following sequence is recommended.